Titlesby GlyphDesign Verification Engineer a new title on company job boards
Engineering · Emerging, unverified · not on Hacker News yet · 19 open roles at 7 companies · median $210k
A design verification engineer creates test environments to validate integrated circuit and hardware designs.
Why it exists
Written by rule from our own data
First seen in our data in June 2021, in a company job-board posting from Baidu. Today 19 open roles use the title at 7 companies, most of them in AI labs.
- PostingThe oldest Design Verification Engineer posting we holdBaidu, Jun 2021 · backs: first sighting
- PostingPrincipal Design Verification Engineer- SerDes/PHY IPAstera Labs, Oct 2026 · backs: an open posting with the title
Where it is posted
Sectors
- AI lab1
- Robotics and autonomy1
Cities
- Palo Alto10
- Tel Aviv, Israel2
- Seattle2
- Bengaluru, India1
- Toronto, Canada1
- San Francisco1
Countries and remote
- United States15
- Israel2
- India1
- Canada1
Posted pay
Middle half $195k to $238k, median $210k from 9 postings that state a base range (USD a year).
Who is hiring for it
Open postings on their own job boards, read 5h ago| # | Company | Open roles | |
|---|---|---|---|
| 1 | 8 | ||
| 2 | K2 SpaceA company hiring most for Design Engineer and Test Engineer. | 4 | |
| 3 | 3 | ||
| 4 | 1 | ||
| 5 | 1 | ||
| 6 | VoltaiA company hiring most for Research Engineer and Forward Deployed Engineer. | 1 | |
| 7 | 1 |
Open roles
8 of 19; company pages list the restPrincipal Design Verification Engineer- SerDes/PHY IP
San Jose, California, United States
| Role | |||
|---|---|---|---|
| Principal Design Verification Engineer- SerDes/PHY IP | San Jose, California, United States | $207k to $230k | |
| Principal ASIC Design Verification EngineerK2 SpaceSeattle, WA$190k to $285k | K2 Space | Seattle, WA | $190k to $285k |
| ASIC Design Verification Engineer | Mountain View, CA, USA | $175k to $215k | |
| Design Verification Engineer | San Francisco | $226k to $445k | |
| Staff Design Verification Engineer | Sunnyvale, CA | Not stated | |
| Design Verification EngineerVoltaiPalo Alto Office | Voltai | Palo Alto Office | Not stated |
| Design Verification Engineer | Sunnyvale,CA | Not stated | |
| Senior Design Verification Engineer | San Jose, California, United States | $149k to $165k |
Related titles
About this title
A design verification engineer creates test environments to validate integrated circuit and hardware designs.
19 open postings titled "Design Verification Engineer" at OpenAI, Waymo, baidu, astera-labs and 3 more (job-board scan, 2026-11-09; proposed by the model). One of the postings. Not checked by hand yet.
Median posted salary $210k from 9 postings that state a base pay range (the median of their midpoints, USD a year). Not a survey of what people earn.